1. Field of the Invention
The present invention relates to a semiconductor storage device.
More specifically, the present invention relates to the structure for performing precharge when data is read out in a DRAM which is a semiconductor storage device.
2. Description of Related Art
A DRAM is known as a memory device. In typical, signal charge amount stored in the DRAM is quite small. Accordingly, in order to detect and amplify the signal charge amount of the DRAM and externally read it out, potential change of bit lines needs to be sensed with high sensitivity.
As more and more devices have been miniaturized in recent years, power supply voltage Vcc applied to the devices needs to be lowered in terms of maintaining operation reliability.
By the way, a Vcc/2 precharge system has typically been employed to read out data of DRAM.
This is disclosed, for example, in ISSCC 2002/SESSION 9/DRAM AND FERROELECTRIC MEMORIES/9.3, A 300 MHz Multi-Banked eDRAM Macro Featuring GND Sense, Bit-Line Twisting and Direct Reference Cell Write, FIG. 9.3.2. However, the following problems are raised if the voltage is lowered in a simple way with the Vcc/2 precharge system.
In the Vcc/2 precharge system, when the reading operation is completed, the potential of the bit lines is equalized and is precharged to the potential of Vcc/2 again.
In the DRAM using such a Vcc/2 precharge system, the voltage between gate and source (Vcc/2) in sense amplifier operation of the transistor that forms a sense amplifier inevitably decreases as the power supply voltage is made lower. As a result, the sense operation is greatly delayed, or may not be performed in a worst case.
For example, when Vcc=1.5 V, the voltage between gate and source (Vcc/2) of a sense amplifier transistor is 0.75 V. In practice, it is expected that the voltage decreases due to resistance of a common source line of the sense amplifier transistor, and especially in initial sensing, the voltage between gate and source is further reduced (to about 0.5 V or less).
Meanwhile, an absolute value |Vth| of a threshold voltage Vth of the sense amplifier transistor needs to be at least 0.3 to 0.5 V in order to guarantee cut-off characteristics. Further, in initial sensing, the substantial value of |Vth| is further increased in accordance with the substrate effect of the sense amplifier transistor.
Hence, the threshold voltage and the voltage between gate and source of the sense amplifier transistor in the initial sense operation are extremely close to each other. Then, the initial sense operation is considerably delayed, which is the biggest obstacle for realizing high-speed DRAM.
On the other hand, a ground precharge system has been used in recent years as a reading method by lowering the bias level of the sense amplifier. In case of the DRAM with the ground precharge system, upon completion of reading operation, the potential of the bit lines is equalized and precharged to the potential of GND. In the DRAM with such a ground precharge system, the voltage between gate and source of the sense amplifier transistor can be doubled compared with the Vcc/2 precharge system, whereby high-speed operation and stability can be maintained in the sense operation even when the power supply voltage is made lower.
Now, the configuration of the DRAM according to the related art using the ground precharge system will be described in brief.
FIG. 4 is a block diagram showing the schematic configuration of a DRAM.
FIG. 5 is a diagram showing the configuration example of a bit line precharge circuit, a reference cell, and a memory cell.
The DRAM includes a memory cell array 700.
The memory cell array 700 includes a plurality of word lines and a plurality of bit lines arranged in matrix. Then, a memory cell is arranged at each intersection of the word lines with the bit lines, and memory cells 2 are arranged in matrix.
Note that, in FIG. 5, only one bit line pair is shown for the sake of simplicity.
The DRAM further includes a decoder 600. The decoder 600 decodes control addresses A0 to Am input through an input buffer 500, and generates a memory cell selection signal WL for selecting a specific memory cell. The decoder 600 further includes a function of selecting a word line and a dummy word line connected to the specific memory cell and a reference cell that forms a pair with the specific memory cell, respectively, based on the memory cell selection signal WL, sensing data that is output or rewriting data, and performing reading/writing data from/to the specific memory cell.
The DRAM further includes a sense amplifier 200.
The sense amplifier 200 detects a difference between charge transmitted from a data storing cell capacitor Cs of the memory cell 2 and charge transmitted from a capacitor Cd in the reference cell when performing reading operation of the memory cell 2 that is selected by the decoder 600. Hence, the sense amplifier 200 reads out data in the memory cell 2.
The data read out in the sense amplifier 200 is amplified to a certain level by a main amplifier 300, and thereafter externally output as digital I/O data DQ0 to DQn through an I/O buffer 400.
Next, a precharge circuit will be described.
The bit line precharge circuit is a transistor circuit for precharging a pair of bit lines BL, BLB for selecting a specific memory cell to about a ground level.
Note that BLB indicates a bar signal of the bit line BL.
The bit line precharge circuit is formed of three bit line precharging transistors 210, 220, and 230. The transistors 210, 220, and 230 of the bit line precharge circuit are NMOS transistors. Then, each of a source and a drain of the NMOS transistor 230 is connected to a pair of bit lines BL, BLB, respectively.
Further, a drain of the bit line precharging transistor 210 is connected to one bit line BLB, a drain of the bit line precharging transistor 220 is connected to the other bit line BL, and sources of the bit line precharging transistors 210, 220 are connected to a common node.
To this common node, ground level of output voltage for precharging is applied.
Further, a precharge activation signal φs is input to each gate of the three bit line precharging transistors 210, 220, and 230.
Further, a reference cell precharging transistor Trc is provided to precharge the reference potential storing capacitor Cd to potential of about Vcc/2. Voltage for precharging the reference cell (Vcc/2) is applied to a source (or drain) of the reference cell precharging transistor Trc. Further, the precharge activation signal φs is input to a gate of the reference cell precharging transistor Trc.
Next, a memory cell array will be described.
One given memory cell which is a component of the memory cell array 700 has one transistor and one capacitor. This memory cell is composed of a cell transistor Tc formed of one NMOS transistor and one data storing cell capacitor Cs.
The operation of such a DRAM device will now be described.
The following operation is performed in order to write data “1” or data “0” to the memory cell 2 through the bit lines BL, BLB.
First, boosted voltage is supplied from the word line WL to the gate of the cell transistor Tc to set the cell transistor Tc to the operation state. Then, charge is stored in the data storing cell capacitor Cs in accordance with “0” or “1” of data.
Further, the following operation is performed to read out data by selecting the memory cell.
Boosted voltage is supplied to the gate of the cell transistor Tc and the gate of the reference cell transistor Tr from the word line WL and the dummy word line DWL, respectively, so as to set the cell transistor Tc and the reference cell transistor Tr to the operation state.
Then, charge stored in the data storing cell capacitor Cs and the reference potential storing capacitor Cd is reallocated through a pair of bit lines BL, BLB.
At this time, the potential of the pair of bit lines BL, BLB is changed.
This potential change of the bit line pair BL, BLB is detected by a sense amplifier.